Construct a full$-$adder and try it out with different inputs. Save your circuit.

Submit: a screenshot of the circuit.

Please save your work. It will be needed for for part $2.$

Suggestion: use the full$-$licensed software, so you can save your file and re$-$open it for part $2.$

IF you cannot work in the CSE lab, download the free trial version for $30-$days free access so you can save your work.

IF you don't even want to download the free trial version and insist to use the web$-$based simulator, be aware your work cannot be saved. Once you close the webpage, your work is lost.

$2.$ Re$-$use the full$-$adder you constructed in part $1$ and construct the $4-$bit adder without overflow detection. Save your work.

Note: to re$-$use the full$-$adder $(1-$bit$),$ refer to the instructions on how to custom your full$-$adder for reuse.

Submit: a screenshot for the circuit. Note: this circuit works for both signed and un$-$signed numbers.

$3.$ Add the overflow detection to the $4-$bit adder: add an output V $=$ C$3$ XOR C$4.($V$=1,$ overflow detected; V$=0,$ no overflow.$)$ Save your work.

Setting values of inputs A and B based on the table below, observe outputs of the circuit and complete the table by filling out S $($sum$),$ C$4($carryout bit$),$ and whether there is an overflow or not.

A B S C$4$ V Overflow$($Yes$/$No$?)$

$00010010001100$ N

$11101110$

$00111011$

$01010011$

$10111101$

Submit: the completed table and a screenshot of the circuit.

Part B:

Re$-$use the $4-$bit adder in part A and construct a $4-$bit adder$/$subtractor for signed numbers. Save your work.

Changing the input signals of your circuit to complete the following table by filling out the sum, carryout bit, and whether there is an overflow or not.

A

B

M

$S$

C$4$ V

CircuitResult translate

Submit: the completed table and a screenshot of the circuit.

Note the limitation of $4-$bit adder$/$subtractor: it can only contain the result in the range of $-8+7.$ Overflow can occur frequently. So we want to extend this circuit to $8-$bit.

Part C: Re$-$use the circuit in Part B and construct an $8-$bit adder$/$subtractor$.$

Submit: a screenshot of the circuit.

Submit: a screenshot of the circuit.

Please save your work. It will be needed for for part $2.$

Suggestion: use the full$-$licensed software, so you can save your file and re$-$open it for part $2.$

IF you cannot work in the CSE lab, download the free trial version for $30-$days free access so you can save your work.

IF you don't even want to download the free trial version and insist to use the web$-$based simulator, be aware your work cannot be saved. Once you close the webpage, your work is lost.

$2.$ Re$-$use the full$-$adder you constructed in part $1$ and construct the $4-$bit adder without overflow detection. Save your work.

Note: to re$-$use the full$-$adder $(1-$bit$),$ refer to the instructions on how to custom your full$-$adder for reuse.

Submit: a screenshot for the circuit. Note: this circuit works for both signed and un$-$signed numbers.

$3.$ Add the overflow detection to the $4-$bit adder: add an output V $=$ C$3$ XOR C$4.($V$=1,$ overflow detected; V$=0,$ no overflow.$)$ Save your work.

Setting values of inputs A and B based on the table below, observe outputs of the circuit and complete the table by filling out S $($sum$),$ C$4($carryout bit$),$ and whether there is an overflow or not.

A B S C$4$ V Overflow$($Yes$/$No$?)$

$00010010001100$ N

$11101110$

$00111011$

$01010011$

$10111101$

Submit: the completed table and a screenshot of the circuit.