Construct the CMOS logic circuit that implements Y = a +a+b+cb using the fewest possible transistors....

Transcribed Image Text:

Construct the CMOS logic circuit that implements Y = a +a+b+cb using the fewest possible transistors. You are allowed to use inverted inputs (e.g., a) rather than adding inverters to create these signals. A CMOS metal layer with resistivity, p, 3x1062-cm is 0.6μm thick. It is used to draw a signal trace that is 100μm long and 0.75μm wide. a) Calculate the sheet resistance, Rs, of this metal layer. b) How many "squares", n, are in the signal trace? c) Use the results in (a) and (b) to determine the resistance of the trace. Construct the CMOS logic circuit that implements Y = a +a+b+cb using the fewest possible transistors. You are allowed to use inverted inputs (e.g., a) rather than adding inverters to create these signals. A CMOS metal layer with resistivity, p, 3x1062-cm is 0.6μm thick. It is used to draw a signal trace that is 100μm long and 0.75μm wide. a) Calculate the sheet resistance, Rs, of this metal layer. b) How many "squares", n, are in the signal trace? c) Use the results in (a) and (b) to determine the resistance of the trace.

Answer rating: 100% (QA)

a The sheet resistance Rs of a metal layer is given by Rs pt where p is the resistivity of the metal ... View the full answer