Construct the Finite State Machine representation for a counter with a cycle length of 4 - i.e a circuit that

counts 0 1 2 3 (output as a binary value, obviously) with successive clock pulses, and then starts over.

The external output is the 2-bit count.

The only external input is R, a reset pulse: when R = 1 it resets the next count to 0, no matter what the

current state (count); when R = 0 it does nothing (i.e. it allows the FSM to transition to the next state in

sequence).

Then construct the complete truth table for the device, showing

the inputs: "current state" labels d*[1:0], and R

the outputs: "next state" labels d[1:0], and the 2-bit count c[1:0]

(Hint: if you choose the state labels sensibly, outputs d and c will actually be the same)

Finally, derive and simplify the algebraic expression for c[0] (i.e. bit 0 of the output).