Could you help me doing this please? Computer Archeticter

See Lecture 21 for method and sample. Given the following sequences of word addresses, in decimal, 1, 4, 2, 7, 21, 4, 27, 3, 5, 24, 28, 19, 57, 1, 27, 3,11 (no modification needed, just convert to binary 1 is 000001, 56 is 111000, etc, these are memory addresses) 1) Simulate an 8 word cache with one word per block, direct mapped. a) For each address, 1ist the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. 2) Simulate a 16 word cache with four words per block, direct mapped a) For each address, 1ist the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. Typical format for partial data at end of sequence eight word cache one word per block sixteen word cache four words per block data v tag data 000I 00I 010I 011 110011 (11)| 100I 1011I 110|I v tag 00 01 1011 00| I 01| I 10 008) 9) (10) (11) Make list of addresses in proper format, indicate H for hit, M for miss last line of each: addr tag ix addr tag 1x word 001 011 M 00 10 11 M The last address, decimal 11, has its contents shown in the cache (You do not get points for this entry.)