CPU TIMING DIAGRAM $($part $1)$

Note that this block diagram is only for reference, it is not needed to complete the exercise

The timing diagram is based on the signal names from the above block diagram, and represents the timing relationship of the signals for either a read or write operation

The address and data bus, A and $D,$ have multiple lines so show as numbers $19-0$ or $7-0.$ The idea is lines $7-0$ are shared between address and data so have different active times on the bus. Therefore, the latch holds the address to the address decoder when the data is active

$\backslash$table$[[$Map the letters from the timing diagram on right of the table below$],[$SIGNAL TIMING EVENT,$\backslash$table$[[$MATCHING LETTER$],[$FROM THE DIAGRAM$]]],[$Address Latched,$],[$Chip Selected $($RAM or ROM$),],[$CPU Instruction Begins,$],[$First Point to Identify Operation Type $($Read or Write$),],[$Data Latched into RAM $($write$)/$ CPU $($read$),],[$CPU Instruction Ends,$]]$