A benchmark in a 5-stage pipelined processor that uses a BTB has the following characteristics:

27% ALU instructions,

24% Load instructions,

23% of instructions are followed by another instruction that needs data being loaded. From these instructions

From these instructions, 17% are branch instructions that need data to determine the branch condition.

12% store instructions,

24% branch instructions (58% of these branches are taken).

13% jump instructions

The branch target buffer (BTB) for conditional branch and jump instructions has the following features. Branch instruction addresses are found in the buffer (hit rate) 92% of the time. 89% of the time the prediction is right (accuracy). If a branch is not found in BTB the default prediction is not taken. On the other hand, jump instruction addresses are found BTB (hit rate) 81% of the time. Jump instructions are predicted right 68% of the time. Addresses for both branch and jump instructions are known at the end of the ID stage.

a) Please determine the CPI for this processor.

27%	ALU
24%	load
12%	Store
13%	jump

b) Let us assume that a return address stack (RAS) is added to this processor. The jump instructions are classified as follows: 72% are either j or jal instructions and 28% are jr instructions. Now, we have those jump instructions are found in BTB 94% of the time with an accuracy of 96%. RAS hit rate is 96% with an accuracy of 98%. Please determine the new CPI.

27%	ALU
24%	load
12%	Store
24%	branch
13%	jump