Create a new project in Quartus Prime Lite software with thename Ass_1_your first name.
Design using VHDL 2-input AND gate, compile your design usingQuartus Prime Lite software, and then simulate your design for allinput combinations using ModelSim-Altera tools.
Design using VHDL 2-input XOR gate, compile your design usingQuartus Prime Lite software, and then simulate your design for allinput combinations using ModelSim-Altera tools.
Design using VHDL full adder using components of AND gate & XORgate created in 2 and 3 above, compile your design using QuartusPrime Lite software, and then simulate your design for all inputcombinations using ModelSim-Altera tools.
Submit one word of PDF file that includes VHDL codes; and screenshots of RTL viewer, Technology map viewer, and RTL simulationwaveform for the above three designs.

I need an answer in less than an hour ple