creating$\_$pp$.$vhd :$-----------$ Partial Product Generator for Multiplier $---------$

$--$Purpose: Generation of $64(8$x$8)$ partial products for input operands.

$--$Style of modelling: Structural

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

use IEEE.STD$\_$LOGIC$\_$ARITH.ALL;

use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL;

entity creating$\_$pp is

Port $($ A : in STD$\_$LOGIC$\_$VECTOR $(7$ downto $0)$;

B : in STD$\_$LOGIC$\_$VECTOR $(7$ downto $0)$;

Y : out STD$\_$LOGIC$\_$VECTOR $(63$ downto $0))$;

end creating$\_$pp;

architecture Behavioral of creating$\_$pp is

$--$ component declaration

component myAND

port$($a$,$b : in std$\_$logic; y: out std$\_$logic$)$;

end component;

begin

a$0$: myAND port map$($a$(0),$b$(0),$y$(0))$;a$1$: myAND port map$($a$(1),$b$(0),$y$(1))$;

a$2$: myAND port map$($a$(2),$b$(0),$y$(2))$;a$3$: myAND port map$($a$(3),$b$(0),$y$(3))$;

a$4$: myAND port map$($a$(4),$b$(0),$y$(4))$;a$5$: myAND port map$($a$(5),$b$(0),$y$(5))$;

a$6$: myAND port map$($a$(6),$b$(0),$y$(6))$;a$7$: myAND port map$($a$(7),$b$(0),$y$(7))$;

a$8$: myAND port map$($a$(0),$b$(1),$y$(8))$;a$9$: myAND port map$($a$(1),$b$(1),$y$(9))$;

a$10$: myAND port map$($a$(2),$b$(1),$y$(10))$;a$11$: myAND port map$($a$(3),$b$(1),$y$(11))$;

a$12$: myAND port map$($a$(4),$b$(1),$y$(12))$;a$13$: myAND port map$($a$(5),$b$(1),$y$(13))$;

a$14$: myAND port map$($a$(6),$b$(1),$y$(14))$;a$15$: myAND port map$($a$(7),$b$(1),$y$(15))$;

a$16$: myAND port map$($a$(0),$b$(2),$y$(16))$;a$17$: myAND port map$($a$(1),$b$(2),$y$(17))$;

a$18$: myAND port map$($a$(2),$b$(2),$y$(18))$;a$19$: myAND port map$($a$(3),$b$(2),$y$(19))$;

a$20$: myAND port map$($a$(4),$b$(2),$y$(20))$;a$21$: myAND port map$($a$(5),$b$(2),$y$(21))$;

a$22$: myAND port map$($a$(6),$b$(2),$y$(22))$;a$23$: myAND port map$($a$(7),$b$(2),$y$(23))$;

a$24$: myAND port map$($a$(0),$b$(3),$y$(24))$;a$25$: myAND port map$($a$(1),$b$(3),$y$(25))$;

a$26$: myAND port map$($a$(2),$b$(3),$y$(26))$;a$27$: myAND port map$($a$(3),$b$(3),$y$(27))$;

a$28$: myAND port map$($a$(4),$b$(3),$y$(28))$;a$29$: myAND port map$($a$(5),$b$(3),$y$(29))$;

a$30$: myAND port map$($a$(6),$b$(3),$y$(30))$;a$31$: myAND port map$($a$(7),$b$(3),$y$(31))$;

a$32$: myAND port map$($a$(0),$b$(4),$y$(32))$;a$33$: myAND port map$($a$(1),$b$(4),$y$(33))$;

a$34$: myAND port map$($a$(2),$b$(4),$y$(34))$;a$35$: myAND port map$($a$(3),$b$(4),$y$(35))$;

a$36$: myAND port map$($a$(4),$b$(4),$y$(36))$;a$37$: myAND port map$($a$(5),$b$(4),$y$(37))$;

a$38$: myAND port map$($a$(6),$b$(4),$y$(38))$;a$39$: myAND port map$($a$(7),$b$(4),$y$(39))$;

a$40$: myAND port map$($a$(0),$b$(5),$y$(40))$;a$41$: myAND port map$($a$(1),$b$(5),$y$(41))$;

a$42$: myAND port map$($a$(2),$b$(5),$y$(42))$;a$43$: myAND port map$($a$(3),$b$(5),$y$(43))$;

a$44$: myAND port map$($a$(4),$b$(5),$y$(44))$;a$45$: myAND port map$($a$(5),$b$(5),$y$(45))$;

a$46$: myAND port map$($a$(6),$b$(5),$y$(46))$;a$47$: myAND port map$($a$(7),$b$(5),$y$(47))$;

a$48$: myAND port map$($a$(0),$b$(6),$y$(48))$;a$49$: myAND port map$($a$(1),$b$(6),$y$(49))$;

a$50$: myAND port map$($a$(2),$b$(6),$y$(50))$;a$51$: myAND port map$($a$(3),$b$(6),$y$(51))$;

a$52$: myAND port map$($a$(4),$b$(6),$y$(52))$;a$53$: myAND port map$($a$(5),$b$(6),$y$(53))$;

a$54$: myAND port map$($a$(6),$b$(6),$y$(54))$;a$55$: myAND port map$($a$(7),$b$(6),$y$(55))$;

a$56$: myAND port map$($a$(0),$b$(7),$y$(56))$;a$57$: myAND port map$($a$(1),$b$(7),$y$(57))$;

a$58$: myAND port map$($a$(2),$b$(7),$y$(58))$;a$59$: myAND port map$($a$(3),$b$(7),$y$(59))$;

a$60$: myAND port map$($a$(4),$b$(7),$y$(60))$;a$61$: myAND port map$($a$(5),$b$(7),$y$(61))$;

a$62$: myAND port map$($a$(6),$b$(7),$y$(62))$;a$63$: myAND port map$($a$(7),$b$(7),$y$(63))$;

end Behavioral;