CS - Computer Organization. Topic: Pipelining. (If you do write your solutions by hand, please write clearly) Thank you so much.

Please pay close attention to the instructions, this is an important task, that will help me to learn the subject and finally pass the class, I will greatly appreciate the help in this regard. My question is the following:

You must show how you arrived at the answer and circle your final answer where applicable! Problem A man has decided to branch out into hardware design. Being new to the field, he's asking for your help in designing a pipeline of a new processor. Once the processor has been built, he's going to test it with a sample program that contains 105 instructions. (a). If the new processor were a non-pipelined, single cycle design and each instruction took 740 ps to finish, how long would it take to execute the sample program? (b). IF the new processor were a non-pipleined multi cycle design with the longest stage taking 130 ps to finish, how long would it take to execute the sample program? (c). Assume the current state-ofthe-art pipeline has 14 stages. Assume also that the stages are perfectly balanced. How much speedup will it achieve compared to the non-pipelined single cycle processor? Be exact here! (d). Realistically, we cannot achieve ideal speedup due to the overhead of implementing pipelining stages (e.g. imperfectly balanced stages, adding pipeline registers, etc). Does this overhead affect the instruction latency, instruction throughput, or both? For each metric affected, is the effect significant? Why or why not? You must show how you arrived at the answer and circle your final answer where applicable! Problem A man has decided to branch out into hardware design. Being new to the field, he's asking for your help in designing a pipeline of a new processor. Once the processor has been built, he's going to test it with a sample program that contains 105 instructions. (a). If the new processor were a non-pipelined, single cycle design and each instruction took 740 ps to finish, how long would it take to execute the sample program? (b). IF the new processor were a non-pipleined multi cycle design with the longest stage taking 130 ps to finish, how long would it take to execute the sample program? (c). Assume the current state-ofthe-art pipeline has 14 stages. Assume also that the stages are perfectly balanced. How much speedup will it achieve compared to the non-pipelined single cycle processor? Be exact here! (d). Realistically, we cannot achieve ideal speedup due to the overhead of implementing pipelining stages (e.g. imperfectly balanced stages, adding pipeline registers, etc). Does this overhead affect the instruction latency, instruction throughput, or both? For each metric affected, is the effect significant? Why or why not