CSC $268$ Computer Organization

Practice Exercise $7\mathrm{.}2$

Design a $3-$bit parallel load shift register using four T flip$-$flops $($labeled T$1,$ T$2,$ and T$3)$ and a LOAD input. This register should allow loading of parallel data through inputs M$1,$ M$2,$ and M$3$ when LOAD is active, and shift the data to the right on each clock pulse when LOAD is inactive.

a$)$ Create the State Diagram: Show the states of the four flip$-$flops $($Q outputs$)$ when shifting data to the right, including the initial loading of M$1,$ M$2,$ and M$3$

b$)$ Complete the State Table: Using the excitation table for T flip$-$flops, fill out the state table indicating the transitions of each flip$-$flop based on LOAD and the clock signal.

$($Note: The excitation table for a D flip$-$flop needed to complete the table below is provided for you in the Appendix section $($on page $3)$ of this worksheet$).$

$\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline $\backslash$multicolumn$\{3\}\{|$l$|\}\{$Present State$\}$ & Input & $\backslash$multicolumn$\{3\}\{|$l$|\}\{$Next State$\}$ & $\backslash$multicolumn$\{3\}\{|$l$|\}\{$Flip$-$flop inputs$\}\backslash \backslash$

$\backslash$hline $\backslash (\backslash$mathrm$\{$Q$\}\_\{\backslash$mathrm$\{$M$\}1\}\backslash )$ & am$2$ & QM$3$ & L & $\backslash (\backslash$mathrm$\{$O$\}\_\{\backslash$mathrm$\{$m$\}1\}\backslash )$ & OM$2$ & $3$ & $\backslash (\backslash$mathrm$\{$T$\}\_\{\backslash$mathrm$\{$M$\}1\}\backslash )$ & $\backslash (\backslash$mathrm$\{$T$\}\_\{\backslash$mathrm$\{$M$\}2\}\backslash )$ & $\backslash (\backslash$mathrm$\{$T$\}\_\{\backslash$mathrm$\{$M$\}3\}\backslash )\backslash \backslash$

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$1$ c$)$ K$-$Maps and Equations: Using the state transitions, complete the K$-$Map for each flipflop input $(\backslash (\backslash$mathrm$\{$T$\}\_\{\backslash$mathrm$\{$M$\}1\},\backslash$mathrm$\{$~T$\}\_\{\backslash$mathrm$\{$M$\}2\},\backslash$mathrm$\{$~T$\}\_\{\backslash$mathrm$\{$M$\}\}\backslash ))$ and derive the Boolean equations needed for the circuit design.

Note: the equation of a K$-$Map with all $1$ s in the table is equal to $1$

d$)$ Draw the Logic Circuit: Design the full circuit diagram with T flip$-$flops and the logic gates required to achieve the parallel load and shift functionality.