Custom Problem #$2($Truth table to PLA Implementation$)$:

$($a$)$ From the truth table you made in Custom Problem #$1($referenced below$),$ implement the function at the

gate level using a PLA.

$($b$)$ Assuming the same gate delays as Custom Problem #$1,$ what is the gate delay of your

PLA implementation

$($c$)$ In terms of speed, which implementation is better? In terms of area on chip, which

implementation is better?

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Custom Problem #$1($Boolean Function to Basic Gate Implementation$)$:

Given the Logic Function: Y$=($A$+$B$+$C$)**($A$^(\text{'})+$B$^(\text{'})+$C$)**($A$+$B$^(\text{'})+$C$)$

$($a$)$ Generate a truth table for the function $($rows of table must be in numerical order$)$

$($b$)$ Using the basic gates: NOT, AND, OR$,$ implement the function at the gate level $($not

transistor level$).$

$($c$)$ If AND gates have a delay of $2\mathrm{.}5$fs$,$ OR gates have a delay of $3$fs$,$ and Inverters have a

delay of $1$fs$,$ what is the total delay of your circuit?