D $7\mathrm{.}103$ Figure P$7\mathrm{.}103$ shows a variation of the feedback$-$bias circuit of Fig. $7\mathrm{.}52.$ Using a $3-$V supply with an NMOS transistor for which $V_1=0\mathrm{.}8V,k_n=4m\frac{A}{V^2},$ and $=0,$ provide a design that biases the transistor at $I_D=0\mathrm{.}5$ mA $,$ with $V_{DS}$ large enough to allow saturation operation for a $1-$V negative signal swing at the drain. Use $13M$ as the largest resistor in the feedback$-$bias network. What values of $R_D,R_{G1},$ and $R_{G2}$ have you chosen? $[$Hint$]$ Just chose $V_{DS}$ large enough for a $1$ V signal swing at the drain. To decide $V_D,$ you can first ignore $I_G$ as it's much smaller than $I_0$; when you get all calculated bias points you can then check to see if your assumption of ignoring $I_G$ is valid or not