Question: (d) Consider the signal from the bus interface to an L1 individual cache to be a 'Read Miss', and the state of the cache

(d) Consider the signal from the bus interface to an L1 individual cache to be a 'Read Miss', and the state of the cache block as 'Shared'. Suppose that this L1 individual cache has the required memory block. Why should the slower L2 cache be allowed to service the request? (e) Consider the signal from the bus interface to an L1 individual cache to be a 'Write Miss', and the state of the cache block as 'Shared'. Can a situation arise where this L1 individual cache does not have the required memory block? Explain briefly. If such a situation can indeed arise, what should this L1 cache controller do?

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