ddacddQ$3)[2$ points$]$ A $4-$bit serial in$/$parallel out shift register is initially set to $1111.$ The

data $1010$ is applied to the input. After three clock cycles the output will

be

$0101$

Q$4)[2$ points$]$ Assume that a $4-$bit serial in$/$serial out shift register is initially clear. Bits

are shifted in from the left. We wish to store $1100.$ What will be the $4-$bit pattern after

the second clock pulse?

$0000r$