Decoding: Given the decoding circuit below, for a 21-bit address version of the MC68008 and knowing that Rxy stands for Reserved or unused space, answer the flooding questions What is the portion size of R11, ROM, and PIO What is the address range of ROM, RAM, R21, PIO, SIO and R32 If ROM is 32 KB, how many address map to each location - What is the logic function of the box X - If the propagation delay of the gate is 3 ns, what is the total decoding delay - If the ROM access time is 70 ns and the ROM access time is 300 ns, find the maximum zero-wait frequency if the Address Strobe Latency is 50 ns, and the Data Latch setup time is 10 ns Find the number of wait cycles to be use with the ROM for the processor ton run at 20 MHz - Write the logic equation of VPA* DTACK* IACK* and BERR* (writing to ROM or accessing any reserved space) Al6A YO A15 B Yi Y2 Y3 PIO* SIO* R31* R32* A18A YO A17B YI Y2 Y3 ROM* RAM* R21* A20A YO B YI Y2 R11* R12* R13* A19 Y3 AS* DS* Decoding: Given the decoding circuit below, for a 21-bit address version of the MC68008 and knowing that Rxy stands for Reserved or unused space, answer the flooding questions What is the portion size of R11, ROM, and PIO What is the address range of ROM, RAM, R21, PIO, SIO and R32 If ROM is 32 KB, how many address map to each location - What is the logic function of the box X - If the propagation delay of the gate is 3 ns, what is the total decoding delay - If the ROM access time is 70 ns and the ROM access time is 300 ns, find the maximum zero-wait frequency if the Address Strobe Latency is 50 ns, and the Data Latch setup time is 10 ns Find the number of wait cycles to be use with the ROM for the processor ton run at 20 MHz - Write the logic equation of VPA* DTACK* IACK* and BERR* (writing to ROM or accessing any reserved space) Al6A YO A15 B Yi Y2 Y3 PIO* SIO* R31* R32* A18A YO A17B YI Y2 Y3 ROM* RAM* R21* A20A YO B YI Y2 R11* R12* R13* A19 Y3 AS* DS*