Question: Question 2: Sequential Logic (15 points) a) Fill the truth table of the given sequential logic circuit. Assume that (1) Q is the value of

 Question 2: Sequential Logic (15 points) a) Fill the truth table
of the given sequential logic circuit. Assume that (1) Q is the

Question 2: Sequential Logic (15 points) a) Fill the truth table of the given sequential logic circuit. Assume that (1) Q is the value of the output after the circuit have been given enough time to produce the output according to the inputs, (2) the inputs A, B and C will always retum back to 000 after every operation, (3) when the inputs return back to 000, they will not transit any of forbidden input combination(s). If you feel the older Q value will be preserved by the input combination, put "Latch" in the table for the output Q. (7 points) Input Output A B Q 0 0 0 Latch 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 5 .SUNMobile 4G @ 13% 1 T9:21 course.cse.ust.hk 1 1 1 6/6 b) A circuit composed of 3 rising edge-triggered D flip-flops connected as shown below. Ignore propagation delays. Assuming the output Q. Q, and : of D flip-flops are all initially. Complete the timing diagram below for the outputs of this circuit, and state what the circuit does with respect to the Childeck) input by referring to the timing diagram 18 points) 294 cur - TTTTTTTEE Q. q_ Question 2: Sequential Logic (15 points) a) Fill the truth table of the given sequential logic circuit. Assume that (1) Q is the value of the output after the circuit have been given enough time to produce the output according to the inputs, (2) the inputs A, B and C will always retum back to 000 after every operation, (3) when the inputs return back to 000, they will not transit any of forbidden input combination(s). If you feel the older Q value will be preserved by the input combination, put "Latch" in the table for the output Q. (7 points) Input Output A B Q 0 0 0 Latch 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 5 .SUNMobile 4G @ 13% 1 T9:21 course.cse.ust.hk 1 1 1 6/6 b) A circuit composed of 3 rising edge-triggered D flip-flops connected as shown below. Ignore propagation delays. Assuming the output Q. Q, and : of D flip-flops are all initially. Complete the timing diagram below for the outputs of this circuit, and state what the circuit does with respect to the Childeck) input by referring to the timing diagram 18 points) 294 cur - TTTTTTTEE Q. q_

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