Question: Derive the expression for the sub - threshold slope ( SS ) of a ( planar ) field effect transistor ( FET ) . What

Derive the expression for the sub-threshold slope (SS) of a (planar) field effect
transistor (FET). What is the minimum sub-threshold slope that can be achieved at room
temperature, and at 85C?
Compute how the SS will change as the gate oxide (SiO2) thickness is reduced from 10nm
to 3nm (at room temperature)?

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