Question: Derive the state diagram and Design a Controller unit for the DataPath unit shown here to implement the arithmetic operation: result=4X-Y. Use Verilog code and

Derive the state diagram and Design a Controller unit for the DataPath unit shown here to implement the arithmetic operation: result=4X-Y. Use Verilog code and Xilinx ISE ISIM to describe/model, simulate and verify the complete digital system that include both the Control and Datapath Unit.

Pls help me with Verilog ASAP. thank you

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