Design a $16-$bit program counter $($PC$)$ that supports features to: $(1)$ increment the current PC value for

the next clock cycle; $(2)$ load a new value into the PC for the next clock cycle; and $(3)$ reset the PC to

zero for the next clock cycle. You may design the PC using the various built$-$in chips available under

nand$2$tetris$/$tools$/$builtInChips$,$ including the Inc$16$and Register$16$chip parts.

You have been provided with the PC$.$hdl file as a starting point to develop your solution. Your chip

design will be tested using the supplied PC$.$tstfile. When loaded into the hardware simulator, PC$.$tst

loads your HDL design, and supplies a battery of test inputs to it and stores the output responses in PC$.$out.

Contents of PC$.$outmust match the outputs listed in the supplied PC$.$cmpfile exactly. If not, the simulator

will display an error.