Design a $2-$level paging scheme for a $38-$bit virtual space with the following configuration:

Each physical page is of size $16$K bytes and each page table entry uses $4$ bytes. Each

$38-$bit virtual address is translated into a $38-$bit physical address. How should the bits of

a virtual address be divided in conducting address translation?

a$)$ The $38-$bit address should be split as $14,12,12$

b$)$ The $38-$bit address should be split as $12,14,12$

c$)$ The $38-$bit address should be split as $12,12,14$

d$)$ The $38-$bit address should be split as $24,14$