Design a 3-digit lock circuit such that the lock opens (-0) when 3-digit passcode pressed sequentially...

  

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Design a 3-digit lock circuit such that the lock opens (-0) when 3-digit passcode pressed sequentially and closed (-1) otherwise. The passcode is the rightmost 3 digits of your student ID. Example the pass code is 912 for student ID 210202912. The circuit has 10 inputs each 1-bit. Each input represents a decimal number 0-9 as shown in the picture. 1. Write the Verilog code in EDAplayground, Save it as "Public". Share the http link of the code here: 2. (50 points) Paste the design code inside this rectangle: 3. (50 points) Write the test bench in EDAplayground and paste the testbench code and the test output inside this rectangle. First, enter 3 wrong digits with #5 delay. If no key pressed or a pressed key released, 10 input bits become 0 (zero). 10 input bits has to become zero between each digit pressing. 4. Bonus: (20 points) Synthesize the Verilog code using EDAplayground by selecting Yosys 0.9.0 Copy paste the diagram here and implement the designed circuit using Digital logic simulator and paste the Digital logic simulator circuit diagram. Note: Rename the word file as studentid.docx (example 210202912.docx) and upload into the LMS system. Bonus: Upload the Digital logic simulator file, studentid.dig into LMS system 5678 AWN40 3-Digit Lock Lock 3 000 Design a 3-digit lock circuit such that the lock opens (-0) when 3-digit passcode pressed sequentially and closed (-1) otherwise. The passcode is the rightmost 3 digits of your student ID. Example the pass code is 912 for student ID 210202912. The circuit has 10 inputs each 1-bit. Each input represents a decimal number 0-9 as shown in the picture. 1. Write the Verilog code in EDAplayground, Save it as "Public". Share the http link of the code here: 2. (50 points) Paste the design code inside this rectangle: 3. (50 points) Write the test bench in EDAplayground and paste the testbench code and the test output inside this rectangle. First, enter 3 wrong digits with #5 delay. If no key pressed or a pressed key released, 10 input bits become 0 (zero). 10 input bits has to become zero between each digit pressing. 4. Bonus: (20 points) Synthesize the Verilog code using EDAplayground by selecting Yosys 0.9.0 Copy paste the diagram here and implement the designed circuit using Digital logic simulator and paste the Digital logic simulator circuit diagram. Note: Rename the word file as studentid.docx (example 210202912.docx) and upload into the LMS system. Bonus: Upload the Digital logic simulator file, studentid.dig into LMS system 5678 AWN40 3-Digit Lock Lock 3 000

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