Design a $4-$bit by $3-$bit Binary Multipler

In this part of the lab, you are required to design a multiplier, which does the

multiplication of a $3-$bit number $B(2$:$0)$ by a $4-$bit number $A(3$:$0).$

The multiplication process can be illustrated as follows:

You are required to use full adders as well as AND gates to implement

this multiplier.

In your lab report, design the multiplier and draw the schematics of your

design.

Write a Verilog module named multiplier $4by3$ to implement your design

from Step $12.$

Write a test bench to use a few simple inputs to test the functionality of

your multiplier, e$.$g$.$ multiply the decimal equivalents: $82,113,$ etc.

Simulate the circuit using Vivado's Simulator and analyze the resulting

waveform. Debug and make any needed corrections should your

multiplier fails to give the correct results. Include descriptions of the

corrections you made, if any, in your lab report.

Once you have verified your design logically$,$ modify the test bench in

Step $14$ to have your multiplier conduct the following multiplications,

use a table to list your inputs and outputs.

$53$

$15x5$

$97$

$157$