Design a $4-$Stage Serial$-$In Serial$-$Out Shift Register using $74$LS$76$ J$-$K flip$-$Flops. Structure your design so that the data is shifted $($appears at the Q output of the next stage$)$ on the leading edge of the clock. Use NAND gates for any required inverters. Note from the data sheet that the $7476$ is a master$-$slave configuration. The data is moved into the master on the leading edge of clock and the flip$-$flop output $($the slave$)$ changes state on the trailing edge of clock.

Verify the $4-$Stage Serial Shift Register using Multisim. Use a Clock Frequency of $1$ Hz $,$ and use a switch to manually toggle the input of the Shift Register to shift bits into the device. Use a digital Oscilloscope to examine the output waveform of the Shift Register.

Design a $4-$Stage Bi$-$Directional Serial$-$In Serial$-$Out Shift Register using $74$LS$76$ JK Flip$-$Flops and NAND Gates. Structure your design so that the data is shifted on the leading edge of the clock.

Verify the $4-$Stage Bi$-$Directional Serial$-$In Serial$-$Out Shift Register using Multisim. Use a Clock Frequency of $1$ Hz $,$ and use switches to manually toggle the inputs of the Shift Register to shift bits into the device. Use a digital Oscilloscope to examine the output waveforms of the Shift Register.