Design a custom single-purpose processor for a system that counts the number of times that input button B is pressed and always outputs that number unsigned on a 16-bit output C, which is initially 0. A press is detected as a change from 0 to 1 the duration of that 1 does not matter. Assume the system count rolls over when the maximum value of C is reached. Capture FSMD and draw the FSMD state diagram for this system. Separate the FSMD into an FSM+D, this means show the data-path. Derive the FSM logic using truth tables and K-maps to minimize logic. Draw your FSM (the controller design) and datapath connections. Write the VHDL code for this custom single-purpose processor