Design a digital system that controls traffic lights. The system generates the color of

the traffic light according to parameters. There is only one output of the

system, light$\_$o$,$ that changes its value between RED, YELLOW, and GREEN

synchronously with respect to the rising edge of the system clock input signal,

named clk$\_$i$.$

The light$\_$o signal should follow the sequence of RED $$ YELLOW $$ GREEN $$

YELLOW $$ RED continuously when updating the color of the traffic light.

The system also incDesign a digital system that controls traffic lights. The system generates the color of the traffic light according to parameters. There is only one output of the system, light$\_$o$,$ that changes its value between RED, YELLOW, and GREEN synchronously with respect to the rising edge of the system clock input signal, named clk$\_$i$.$ The light$\_$o signal should follow the sequence of RED $$ YELLOW $$ GREEN $$ YELLOW $$ RED continuously when updating the color of the traffic light. The system also includes an active$-$high reset input signal, rst$\_$i$,$ synchronous to the rising edge of the clk$\_$i signal. When the rst$\_$i signal is set to logic $\text{'}1\text{'},$ the output resets to the RESET$\_$COLOR state. The following parameters govern the behavior of the system: $$ RED$\_$DURATION, YELLOW$\_$DURATION, and GREEN$\_$DURATION: Represent the durations of the RED, YELLOW, and GREEN lights, respectively. These durations are defined in terms of the number of clk$\_$i cycles. $$ RESET$\_$COLOR: Defines the state of light$\_$o when the reset signal $($rst$\_$i$)$ is asserted to logic $\text{'}1\text{'}.$ ENABLE$\_$YELLOW: A boolean parameter that enables or disables the YELLOW light. When set to $1,$ the light$\_$o signal sequence is RED $$ YELLOW $$ GREEN $$ YELLOW $$ RED. When set to $0,$ the YELLOW color is removed, and the sequence becomes RED $$ GREEN $$ RED. The system must adhere to the following requirements: $$ The light$\_$o output signal should update only on the rising edge of the clk$\_$i signal. $$ Upon assertion of the rst$\_$i signal, the light$\_$o output should immediately reset to the value defined by the RESET$\_$COLOR parameter. Implementation Requirements: $$ Implement the system in Verilog. $$ Develop a testbench in Verilog $($or SystemVerilog$)$ to verify the functionality of your design. The testbench should: o Generate clock and reset signals. o Monitor the light$\_$o output and validate that the sequence and timing match the expected behavior based on the provided parameters. o Include stimulus to test the functionality with ENABLE$\_$YELLOW set to both $1$ and $0.$ o Test the reset functionality and ensure the system resets to RESET$\_$COLOR.

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