Design a Fibonacci number generator that accepts as input a number n on the port numberIn...

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Design a Fibonacci number generator that accepts as input a number n on the port numberIn and output the nth Fibonacci number on the output port numberOut. The nth Fibonacci number is the sum of the (n - 1) and (n-2) Fibonacci numbers, and the first two numbers in the sequence are 0 and 1. So the Fibonacci sequence is: 0, 1, 1, 2, 3, 5, 8, 13, 21,... Your design should accept the input value of n on the port numberIn when a start signal called go is high. The reset signal is active low and should be asyn- chronous. The output consists of the nth Fibonacci number on the port number Out and a done signal of 1 for one clock cycle indicating that the output is valid. The maximum number of n is 24 and hence the 24th Fibonacci number is 46, 368. The Fibonacci numbers generator algorithm can be described in the following C- code: unsigned int fibonacci (int n) { unsigned int previous = 0; unsigned int current = 1; unsigned int tmp; unsigned int count = 1; while (count n) { tmp = current; current = current + previous; previous tmp; count count + 1; return current; } } Your Design You should follow all design steps. Start with the top-level block diagram and identify all external (primary) input and output signals for the whole design. Divide your design into two units: Data Path unit and Control Unit. Identify all the signals to the data path and control unit. . Show the design of the Data Path Unit: Identify the required blocks (i.e., storage elements, functional units, and interconnects) and design them. Show the design of the Control Unit: Identify the required control signals, design the Control Unit, and connect it to the data path. Write Verilog modules for both data path and control unit. Write Verilog module for the whole design. Write a test unit (test bench) to test and simulate your design. Design a Fibonacci number generator that accepts as input a number n on the port numberIn and output the nth Fibonacci number on the output port numberOut. The nth Fibonacci number is the sum of the (n - 1) and (n-2) Fibonacci numbers, and the first two numbers in the sequence are 0 and 1. So the Fibonacci sequence is: 0, 1, 1, 2, 3, 5, 8, 13, 21,... Your design should accept the input value of n on the port numberIn when a start signal called go is high. The reset signal is active low and should be asyn- chronous. The output consists of the nth Fibonacci number on the port number Out and a done signal of 1 for one clock cycle indicating that the output is valid. The maximum number of n is 24 and hence the 24th Fibonacci number is 46, 368. The Fibonacci numbers generator algorithm can be described in the following C- code: unsigned int fibonacci (int n) { unsigned int previous = 0; unsigned int current = 1; unsigned int tmp; unsigned int count = 1; while (count n) { tmp = current; current = current + previous; previous tmp; count count + 1; return current; } } Your Design You should follow all design steps. Start with the top-level block diagram and identify all external (primary) input and output signals for the whole design. Divide your design into two units: Data Path unit and Control Unit. Identify all the signals to the data path and control unit. . Show the design of the Data Path Unit: Identify the required blocks (i.e., storage elements, functional units, and interconnects) and design them. Show the design of the Control Unit: Identify the required control signals, design the Control Unit, and connect it to the data path. Write Verilog modules for both data path and control unit. Write Verilog module for the whole design. Write a test unit (test bench) to test and simulate your design.