Design a FIFO that operates using a common clock for reading and writing. It should operate using a reset. The FIFO has input and output data ports, and two$-$bit lines serving as flags to denote the

status of the stack $($full or empty$).$ The FIFO module should not support simultaneous read and write and should give preference to the read operation. Use parameters for the stack height and

width. $($As a starting point, assume that the data width is $5$ and the stack height is $8)$

Create a test$-$bench to test the FIFO operation:

$-$ For the testbench use probes to check the contents of the FIFO for testing.

$-$ Make sure you test the flag operations $($full and empty$)$

Show all Verilog code, test bench code, and give explanation of the results.