Design a memory block that operates using a common clock for reading and writing. It should operate using a reset that would clear all the memory content. The RAM memory has input and output data ports, and address lines. The memory module should not support simultaneous read and write and should give preference to the write operation. Use parameters for the memory height and width. $($As a starting point, assume that the data width is $4$ and the stack height is $8).$

Create a test$-$bench to test the memory operation:

For the test$-$bench use probes to check the contents of the memory for testing.

Show all Verilog code, test bench code, and give explanation of the results.