Design a finite state machine to detect the following patterns within an input sequence of 4- bit hexadecimal values. Each 4-bit value is received at every new clock cycle. Pattern 1: Four consecutive values that are equal. (Example 4444 or CCCC are matches and not 42AC). (and) Pattern 2: Four consecutive values with fixed increment. (Eg: 1234 or 26AE and not 53BD, the values do not cycle through, i.e, EF12 is not recognized as fixed increment) A valid sequence of inputs may follow pattern 1 or pattern 2 and is not known ahead of time. The sequence detector upon detecting the pattern outputs a 1 and holds the output until reset signal is given. Draw the finite state transition diagram and design a Mealy or Moore machine to implement the sequence detector.