Design a five stage pipelined processor with necessary combinational logic circuits and sequential logic circuits in Verilog strategy as below:

-The design should meet all data path requirements shown in figure below

-The design should also meet all control signal requirements shown in this figure

-Define the instruction memory as 1024 words of 4-bytes each and the data memory as 1024 doublewords of 8-bytes each.

-For the processor design, include a design description.

-Implement data forwarding as illustrated in this photo