Design a single-cyle processor with necessary combinational logic circuits and sequential logic circuits in Verilog strategy as below:

-The design should meet all requirements shown here

-Define the instruction memory as 1024 words of 32bits each and the data memory as 1024 words of 64bits each.

-Use Verilog code given in Section 5.13 and modify it for ARMv8 and include a test bench module.

-For the processor design, include a design description.