Design a Mealy FSM which functions as a sequence detector, generating two outputs y, z in the following way: a) The signal is applied sequentially to a single input line x. b) Initially both outputs y, z are set to 0. c) Output y is set to 1 when the sequence "10" has been applied to the input x; it should then be reset to 0 and the circuit should continue detecting next occurrence of "10". d) Output z is set to 1 if the sequence containing "10" is followed by "11", that is, when the sequence "1011" has been applied to the input x (at the same time y should stay at 0). Derive a state diagram for this FSM and implement its combinational logic component in two different ways: i) as a PLA; and ii) as a ROM. Make sure to show the complete solution: the state diagram, state table, and the two hardware implementations (PLA and ROM). Make sure to show the content of the PLA and ROM blocks, and show how they are connected to the state registers to form the sequential machine.