Design a mealy sequence detector circuit that has one external input (W) and one output(Z). The circuit produces Z-1 when the previous two values of W were 00 or 11; otherwise Z-0. Use clocked JK flip-flops. a. Write down the excitation table of the JK flip-flop. b. Draw the state diagram of the circuit. c. Specify how many flip-flop required to build this circuit (explain your answer)? d. Build the transition table. e. Plot the k-maps for the flip flop inputs and the circuit output. f. Plot the logic circuit.