Design a memory map for a system with $64K$ of memory space, a $16-$bit address bus, and a $8-$bit data bus. The

system needs to meet the following design requirements:

The system needs $20K$ of ROM, organized in a contiguous block starting at address $0$xA$000.$

The system needs RAM filling the memory range from $0$x$4000$ to $0$x$6$FFF $($inclusive$).$

Your design must be subject to the following constraints in terms of access to memory chips:

You can use a maximum of two $(2)8K8$ RAM chips.

You can use a maximum of two $(2)4K4$ RAM chips.

You can use a maximum of two $(2)8K8$ ROM chips.

You can use a maximum of two $(2)4K8$ ROM chips.

Answer the following questions, and make sure your labels for each chip is consistent.

Design the memory map by identifying the beginning and end addresses $($inclusive$)$ for each chip in hex$-$

adecimal. A table and$/$or a diagram may be helpful here. Giving each chip a name $($like "ROM $0"$ or "Joe"$)$

will be helpful for answering the next two questions. $[4$ marks$]$

Design the chip select logic. Use either ${}_n!a_n,$ or $a_n^{\text{'}}$ to indicate the complement of an address bit, OR give

an explanation for whatever other fancy notation you prefer. Please make sure to somehow identify which

chip from the memory map above corresponds to which logic expression. $[4$ marks$]$

Describe how the address and d$$ta bus are connected to each chip. The data bus can be identified by

$d_7,$dots,$d_0.$ Please make sure to somehow identify which chip from the memory map above corresponds

to which address and data bus connections. $[2$ marks$]$