Design a radix$-28-$bit signed multiplier. The multiplier should take two $8-$bit $2\text{'}$s complement numbers as input and provide a $16-$ bit $2\text{'}$s complement product as the output.

Guidelines:

Provide a complete design for the circuit that supplies the control signals to the multiplexer.

Design the controller as an FSM$.$

Implement the components in VHDL and then integrate the components using port maps to build the full multiplier.

Synthesize the multiplier onto FPGA.