Design a real-time clock using the IP Catalog to generate an appropriate sized (precision) counter core with the desired input control signals. Instantiate it two times and add the required circuit to display the time in MM.SS format on the four 7-segment displays. The design input will be a 100 MHz clock source and a reset signal using the BTNU button. At any time if BTNU is pressed the clock resets to 00.00. Verify the desigrn functionality in hardware using the Basys3 or the Nexys4 DDR board. Design a real-time clock using the IP Catalog to generate an appropriate sized (precision) counter core with the desired input control signals. Instantiate it two times and add the required circuit to display the time in MM.SS format on the four 7-segment displays. The design input will be a 100 MHz clock source and a reset signal using the BTNU button. At any time if BTNU is pressed the clock resets to 00.00. Verify the desigrn functionality in hardware using the Basys3 or the Nexys4 DDR board