Design a sequential circuit that performs division by repeated subtractions. At each clock cycle cct performs subtraction until a stop condition occurs. The number of subtractions have to be stored as the quotient. Remainder has to be stored in a register. Inputs: A(A2A1A0) is dividend, B(B2B1B0) is divisor. Outputs: Q(Q2Q1Q0) is quotient, R(R2R1R0) is remainder. The circuit has to perform the following algorithm: I) Initialize cct: remainder =A and quotient Q=0. II) Enable cct to perform as a sequential cct. III) For each clock cycle circuit performs the subtraction Rn+1=RnB. IV) Rn is stored in a 4-bit register with parallel load. Rn+1 is the output of the subtractor and input of the 4-bit register. V) If Rn>=B, increment Q and assign Rn=Rn+1 with the clock cycle, else hold Rn and Q as the remainder and quotient, respectively. Use a 4-bit subtractor (adder-subtractor of pre\#1 can be used), 4-bit register with parallel load, 4bit comparator and a 4-bit binary counter to store