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Math $211$ Fall $2023$ Lecture $20$

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Question

Design a sequential circuit that performs division by repeated subtraction cct performs subtraction until a stop condition occurs. The number of su stored as the quotient. Remainder has to be stored in a register.

Inputs: $A(A2A1A0)$ is dividend, $B(B2B1B0)$ is divisor.

Outputs: $Q(Q2Q1Q0)$ is quotient, $R(R2R1R0)$ is remainder.

The circuit has to perform the following algorithm:

I$)$ Initialize cct: remainder $=$A and quotient $Q=0.$

II$)$ Enable cct to perform as a sequential cct$.$

III$)$ For each clock cycle circuit performs the subtraction $R_{n+h}=R_n-B$

IV$)R_n$ is stored in a $4-$bit register with parallel load. $R_{n+1}$ is the output of input of the $4-$bit register.

V$)$ If $R_{n}B,$ increment $Q$ and assign $R_n=R_{n+1}$ with the clock cycle, else ho remainder and quotient, respectively.

Use a $4-$bit subtractor $($adder$-$subtractor of pre#$1$ can be used$),4-$bit register bit comparator and a $4-$bit binary counter to store Q$.$

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