Design a state diagram and state table for a sequential circuit that has one synchronous

input $($x$)$ and one output $($ Z $).$ The output begins at $0$ and becomes $1$ when the number of

$1\text{'}$s received and the number of $0\text{'}$s received are both odd. The output returns to $0$ if either

the number of $1\text{'}$s or the number of $0\text{'}$s is even. Below is a sample input and output

sequence:

x$,1,0,0,1,0,0,0,1,1,0,1,0,0$

Z$,0,0,1,0,0,0,0,0,1,0,0,0,1,0$