Design a static CMOS gate to implement the function $F\frac{?}{b}=ar(A*B+C*D*E).$ Size the transistors so that the worstcase pull$-$up and pull$-$down resistance of the gate is equal to that of the smallest inverter in the technology with $\frac{P}{N}$ sizes of $\frac{2}{1}.$ If there are multiple ways of designing, pick a design with the least nominal parasitic delay.

In this technology

$R_p=2\mathrm{.}5R_n$

since it is a $\frac{5}{2}$ inveter

Calculate the Elmore delay for the following transitions. The input word is given by ABCDE. You may assume that no source$/$drain sharing is allowed.

$(00101)(00111)$

$44RC$

Page

$6$

r$/$M $108$

R

a

$+$