Question: Design a synchronous Moore finite state machine using gates and flip flops that will count up from 1 to 3 decimal: 1 2 3 1

Design a synchronous Moore finite state machine using gates and flip flops that will count up from 1 to 3 decimal: 1 2 3 1 2 3 etc. The states should be encoded in binary as: 01 10 11 01 10 11 01 10 11... You must use D flip flops that have only D and clock inputs and a Q output.

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