The FSM Network presents, an Epic Showdown: Moore v$.$ Mealy

A sequential circuit has two inputs X and Y and one output Z$.$ So long as Y$=0,$

then Z$=1$ when an even number of $1\text{'}$s have been received on X$,$ and Z$=0$ when

an odd number of $1\text{'}$s have been received on X$.$ Once Y$=1,$ and forever after, the

behavior flips: Z$=1$ when an odd number of $1\text{'}$s have been received on X$,$ and Z$=0$

when an even number of $1\text{'}$s have been received on X$.$

Draw a Moore state diagram. $($Moore means that the output only depends the

current state.$)$

Assign binary labels to the states following a standard encoding and write the

truth tables for the next state and the output.

Implement the finite state machine using logic gates and D flip flops.

NOTE: please explain the different components of the state diagram i$.$e$.$ if you use two states explain what they mean and what is inside, or if you use four explain why. I used four on this problem, but I get the feeling I am wrong.