Design a synchronous sequential logic circuit that will detect a

defined serial pattern appearing on a single data input. The circuit

has a single output which is a $1$ when the serial input sequence

$1011($X$0$X$1$X$2$X$3)$ is detected. Design the circuit using D flip$-$flops.

a$.$ Draw the state diagram.

b$.$ Develop the state table by assigning binary codes for the states.

c$.$ Write the input$/$output equations from the state table.

d$.$ Derive the simplified Boolean expressions using map reduction.

e$.$ Draw the sequential circuit diagram representation of the Boolean

expressions using D flip$-$flop input and output equations.

f$.$ Is this a Mealy or Moore FSM machine model? Justify your answer.

Z

B

CLK

JA Q

KA

B

A

JB Q

KB

Y

$1$

B