Design a system that accepts its input as three synchronized serial binary data streams A, B, and C, and a clock signal CLK. During each data interval, your system examines the three data bits and creates a fourth bit P such that P=1 if there is an even number of 1s in the data, and P=0 if there is an odd number of 1s (generating an odd parity bit). Finally, your circuit generates a single serial output binary stream OUT, comprising each data bit and the parity bit in turn on the same wire. The process then repeats.