Question: Design a systemverilog code AND testbench for a 4-bitripple carry adder-subtractor.Inputs: A = (A3, A2, A1, A0), B = (B3, B2, B1, B0), modeOutputs: S

Design a systemverilog code AND testbench for a 4-bitripple carry adder-subtractor.Inputs: A = (A3, A2, A1, A0), B = (B3, B2, B1, B0), modeOutputs: S = (S3, S2, S1, S0), carryoutAddition: set inpu 2 answers

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