Design a two$-$stage differential input$-$output amplifier using CMOSP $0\mathrm{.}18$ technology to meet the

following specifications.

Differential pair tail current $=540$uA

Total gain $>300$

Total Power $<mtext></mtext><mn>5</mn>$ mW

Maximum output swing $($the output voltage must be $0\mathrm{.}9$ V when no input signal is applied$)$

Power supply $=1\mathrm{.}8$V

a$)$ Perform simulations to determine the characteristic curves for the provided NMOS and

CMOS transistors. Determine the transistors' output resistance for varying drain currents

and aspect ratios

b$)$ Perform an analytical analysis to estimate the operating point of the transistors and estimate

the gain of each stage.

c$)$ Perform a DC simulation to determine the gain of each stage.

d$)$ Perform AC simulation to find the $-3$ dB bandwidth of the amplifier

e$)$ Apply a differential sinusoidal input with a frequency of $1$ kHz and an amplitude of $1$ mV

to the inputs. Perform transient analysis to calculate the gain.

f$)$ Justify your design decisions and compare your simulation results with the estimated

values from hand calculations.

g$)$ Include a screenshot of the circuit in your report, highlighting the operating points of the

transistors and the voltage values at the relevant nodes.

Important Note: You are not allowed to use resistors or capacitors in your design. You may use

one supply voltage $($vdc from analogLib$)$ and one reference current $($idc from analogLib$).$

$[$Could you design the circuit that should be used in Cadence and how to perform each part of this question and what each part should look like?$]$