Differential Amplifier Design

This project requires designing and simulating a differential amplifier using $180$ nm CMOS

technology in LTSPICE. The amplifier must include a current mirror as an active load, a tail current

source for biasing, and operate with a VDD of $1\mathrm{.}8$ V $,$ a tail current of $1$ mA $,$ and an input signal

amplitude of $0\mathrm{.}1$ mVpp at $10$ kHz $.$ The task involves selecting appropriate transistor dimensions $($W$/$L

ratios$)$ to ensure proper saturation region operation and optimizing resistor or current source values

for the desired bias current. Simulations include DC operating point analysis to verify transistor

operation, AC analysis to determine differential gain $($Ad$),$ common$-$mode gain $($Acm$),$ input$/$output

impedance, bandwidth $(3$dB and unity$-$gain$),$ and transient analysis to observe output waveforms and

verify linearity. The Common$-$Mode Rejection Ratio $($CMRR$)$ must be calculated as CMRR $=$

$20$ log$($Ad$//$Acm$),$ aiming for Ad $>80[$V$//$V$]$ and CMRR $>60$dB while minimizing power

consumption. The design process involves iteratively adjusting dimensions and currents to meet

performance metrics, documenting the effects on gain, CMRR$,$ and other parameters. The project

deliverable includes a detailed report with schematics, simulation results, and analysis of design

choices, including a bonus challenge of comparing performance with a cascode$-$loaded differential

amplifier design.