Design a Verilog model for a counter using a for loop with an output type of reg[4:0]. Figure 5.7 shows the block diagram for the module definition. The counter should increment from 000002 to 111112 and then start over. Use delay in your loop to update the counter value every 10 ns. Consider using the loop variable of the for loop to generate an integer version of your count value, and then assign it to the output variable of type reg[4:0].