Question: Design address decoding circuits for the following 68HC11 sub-systems (do not show MCU, only show memories/ports): -(a) 4KB RAM (two 2KB chips) starting at address

Design address decoding circuits for the following 68HC11 sub-systems (do not

Design address decoding circuits for the following 68HC11 sub-systems (do not show MCU, only show memories/ports): -(a) 4KB RAM (two 2KB chips) starting at address $CO00 [8] -(b) 8KB EPROM (two 4KB chips) starting at address SE000 [6] (c) I/O chip partially decoded to start at $9800 (assume four consecutive addresses for input, output, status and control registers respectively). [6] Design address decoding circuits for the following 68HC11 sub-systems (do not show MCU, only show memories/ports): -(a) 4KB RAM (two 2KB chips) starting at address $CO00 [8] -(b) 8KB EPROM (two 4KB chips) starting at address SE000 [6] (c) I/O chip partially decoded to start at $9800 (assume four consecutive addresses for input, output, status and control registers respectively). [6]

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