Design an 8-Bit up/down counter using behavioral modeling. Your model should define COUNT_SIZE as a parameter and use it in the model. The counter will use the on-board 100 MHz clock source. Use the clocking wizard to generate a 5 MHz clock, dividing it further by a clock divider to generate a periodic one second signal. Define the synthesis attribute to not to use the DSP48 slices. Use the BTNU button as reset to the circuit, SW as enable, SW1 as the Up/Dn (1-Up, 0-Dn), and LED7 to LEDO to output the counter output. Go through the design flow, generate the bitstream, and download it into the Basys3 or the Nexys4 DDR board. Verify the functionality. Fill out the following utilization information after reviewing the Project Summary tab and utilization report